Metal oxide semiconductor (MOS) structures are basic electronic devices used in many integrated circuits. One such structure is the MOSFET, or metal oxide field effect transistor, which is conventionally formed in a semiconductor substrate by providing a gate structure over a channel region provided in a substrate, and by forming doped source and drain regions on opposing sides of the gate structure and the channel region of the substrate.
FIG. 1 illustrates a portion of a conventional MOSFET memory array device 5 comprising a single transistor. A conventional MOSFET memory array device 5 includes a gate structure 10 on a substrate 8. The substrate 8 is conventionally a bulk silicon substrate. The gate structure 10 conventionally includes a gate oxide 12, a conductive polysilicon layer 14, an overlying WSix layer 16, an overlying oxide layer 18 and a Si3N4 capping layer 20. After depositing and patterning Si3N4 capping layer 20, spacers 40, 42 are formed from silicon nitride. Optional oxidized sidewalls 22, 24 may be formed on the gate structure 10, and optional oxide regions 26, 28 may be formed on the substrate 8. An ion implantation step may be performed to form source and drain regions 30, 32, which are both aligned to the edge of the gate structure 10.
To keep pace with the current trend toward maximizing the number of circuit devices contained in a single chip, integrated circuit designers continue to design integrated circuit devices with smaller feature sizes. However, as MOSFET devices are scaled down to the nanoscale region, critical problems can arise. One of the fundamental problems in continued scaling of MOSFETs is the 60 mV/decade room temperature limit for the subthreshold slope.
Devices have been proposed that use impact ionization to switch from the off to the on state. Such impact ionization devices may exhibit a subthreshold slope much lower than kT/q. The basic structure of a conventional impact ionization MOSFET device (I-MOS) 5′ is shown in FIG. 2. A gate stack 10′ is patterned and flanked by offset spacers 43. The source area 46 is masked while the drain 44 is formed. Secondary spacers 50 are formed to create the intrinsic region 52. Then, the drain area is masked while the source area 46 is implanted. While conventional MOSFET devices are doped NPN or PNP (source-drain-channel), I-MOS devices are NNP or PPN with the channel being more lightly doped than the source or drain.
Unfortunately, a planar I-MOS device 5′ requires more space on a chip surface as compared to conventional MOSFET devices having the same gate length. Thus, L-shaped impact ionization transistors were created. However, such L-shaped transistors are formed using a complicated process flow. Conventional I-MOS devices operated at higher voltages than conventional MOSFET devices. Thus, impact ionization regions are preferably formed of germanium or silicon germanium, which lowers the required threshold voltage, but such materials are difficult to incorporate into conventional I-MOS devices using current processing techniques. Thus, it would be desirable to create an I-MOS structure than can be manufactured using a relatively straightforward process flow and of a design that does not exceed, or only slightly exceeds, the dimensions of conventional MOSFET devices.